1. Field of the Invention
This invention relates generally to producing an accurate desired output frequency and channel spacing while using crystals with much lower tolerance requirements than normally required and no “pull ability” requirement. More particularly, it relates to a system and method for producing an accurate desired output frequency and channel spacing using a numerically controlled oscillator (“NCO”) instead of a conventional integer reference divider to generate a reference frequency used in a frequency synthesizer.
2. Background of Related Art
Cord less telephone, cellular, and wireless local area network (“LAN”) and personal area network (“PAN”) and user terminals generally employ frequency synthesizers to generate signals, including transmitter output signals, local oscillators, etc. Each user terminal's synthesizer generates these frequencies based on a local master oscillator, invariably a crystal oscillator. Such crystal oscillators have finite tolerances.
A typical way to synchronize two communicating units has been to make one of the units a timing slave to the other unit. In a digital cord less telephone, for example, a base station may serve as a timing master and a handset may serve as a timing slave. In such an arrangement, the receive timing of the handset may be derived from the base station transmission timing via a signal received by the handset from the base station. The transmit timing of the hand unit may then be derived, for example, from the receive timing as is typical. In this manner, synchronization of the timing among the base station and the handset is achieved.
A typical arrangement for achieving synchronization according to this typical synchronization scheme employs a phase lock loop in the slave unit, presumed herein to be the handset (for purposes of discussion only, and not intended to be limited to that case). The phase lock loop serves to lock on the signal received by the handset and to recover a timing signal, i.e., a clock signal, from that received signal. The received signal itself is then utilized by the handset to dictate the handset timing. In this configuration, transmit timing of the handset is derived directly from the receive timing, and the phase lock loop is employed to compensate for jitter of the received signal and to lock on that signal in order to derive transmit timing. When the received signal so dictates timing of the handset, the handset acts as a timing slave to the base station, thereby resulting in synchronization.
The frequencies generated by user terminals and base/master stations must align accurately for proper system operation and to avoid undue interference to users of adjacent channels. These factors generally result in the necessity to use relatively high precision (and therefore relatively expensive) crystal oscillators in both the user terminals and the base/master stations.
Some current cord less telephone systems use a varactor diode to adjust a frequency of a handset's master oscillator, in combination with a processor-based software algorithm, driven by an estimate or measurement of a frequency offset between a handset and its companion base station, to control a digital-to-analog converter (DAC). The DAC's output is used as a control voltage to the varactor diode to align the handset's master oscillator with that of a companion base station.
A disadvantage of using a varactor diode is that it is frequently an additional external component, along with additional associated passive components, on a printed circuit board (“PCB”), taking up valuable PCB area and adding cost. External varactor diode circuits also subject the master oscillator to a certain degree of vulnerability to external noise modulation of the varactor diode, thus degrading the spectral purity of the handset's master oscillator. Careful design and layout can minimize this latter disadvantage, but the risk still exists, sometimes requiring additional shielding and filtering which further consume PCB area and adds cost.
Additionally, the crystal employed in the handset's master oscillator must be specified for a specific degree of “pull ability”, which adds to the cost and can result in the necessity of employing larger crystal packages than would otherwise be necessary, were it not for the “pull ability” requirement.
FIG. 1 illustrates a conventional circuit utilizing a master crystal oscillator circuit 1 connected to one side of a phase/frequency detector 2. A second input to the phase/frequency detector 2 is produced by the output of modulus control logic 3. A dual modulus prescaler 4 feeds the modulus control logic 3 and receives a signal from the modulus control logic 3. A voltage controlled oscillator 5 outputs to the dual modulus prescaler 4 and receives a filtered control voltage, filtered by low pass filter 6, from the phase/frequency detector 2.
In operation, master crystal oscillator circuit 1 produces a square-wave Fref that is applied to a first input of phase/frequency detector 2. The phase/frequency detector 2 produces a voltage based on the difference between the square-wave produced by master crystal oscillator circuit 1 and the frequency of the signal produced by modulus control logic 3. Phase/frequency detector 2 produces a control voltage that is output to VCO 5. The control voltage contains a ripple component at Fref that causes undesirable sidebands at the VCO 5 output frequency +−Fref. Low pass filter 6 removes the ripple components, suppressing these “reference spurs,” dampens transient responses, such as when changing frequencies, and is used to optimize settling time and other loop parameters. One output from VCO 5 is output to a dual modulus prescaler 4, which alternately divides the frequency produced by VCO 5 by either a P or P+1 value.
Modulus control logic 3 is controlled by two values A and N, where A is always smaller than N. A and N are programmable counters that decrement simultaneously to their terminal counts and are decoded in the modulus control logic to control the dual modulus prescaler's 4 value to be either P or P+1. A represents the number of cycles of the VCO output for which the dual modulus prescaler 4 divides by P+1. N represents the number of additional cycles of the VCO output (after counter A has decremented to its terminal count) that dual modulus prescaler 4 divides by P. A modulus control signal from the modulus control logic block 3 feeds back to the dual modulus prescaler 4 to change its divisor from P+1 to P, and vise versa, according to the state of the divide-by-A and divide-by-N counters. The output of the A counter in the modulus control logic block 3 is the VCO signal divided to Fref, which is applied to the phase/frequency detector 2. In this manner, the control voltage produced by the phase/frequency detector 2 forces the VCO 5 to converge onto a desired frequency.
FIG. 2 illustrates a conventional master crystal oscillator circuit using a digital-to-analog converter 7 connected to a varactor 8. The varactor 8 outputs a control signal to varactor that controls master crystal oscillator 9, whose output is thereafter divided by the “reference divider” 10 to create a reference frequency for a frequency synthesizer.
In operation, the DAC 7 produces a control voltage for varactor 8 based on a software algorithm. The software algorithm can be adjusted during the manufacturing phase of the circuit to compensate for individualistic characteristics of the master crystal oscillator 9. Varactor 8, based on the control voltage produced by DAC 7, adjusts the frequency produced by the master crystal oscillator 9.
The frequency produced by the master crystal oscillator 9 is divided by the divider 10 by a value R. R is typically the channel spacing between the different possible channels available for transmission and reception. A square-wave reference frequency Fref is output from the divider 10 to the phase/frequency detector 2 in FIG. 1.
FIG. 3 illustrates a second conventional master crystal oscillator circuit using a master crystal oscillator 13 connected to an initial calibration adjustment circuit 11, a temperature compensation circuit 12 and a divider 14.
In operation, the initial calibration adjustment circuit 11 is set or programmed during manufacture of the master crystal oscillator circuit to set the master crystal oscillator to operate on the desired frequency at some nominal temperature.
Temperature compensation circuit 12 may be comprised in a variety of ways from a variety of components such as a varistor/resistor bridge or other temperature sensing device, a micro controller, non-volatile memory, a digital-to-analog converter, a varactor, etc. The temperature compensation circuit 12 changes the varactor control voltage value according to variations in temperature to produce a constant output frequency. The varactor performs as the varactor in FIG. 2, wherein the varactor “pulls” the frequency of the master crystal oscillator 13 to adjust the frequency produced by the master crystal oscillator 13.
The frequency signal produced by the master crystal oscillator 13 is divided by divider 14 by a value R. R is typically the channel spacing between the different possible channels available for transmission and reception. The resulting square-wave reference frequency Fref is output from the divider 14 to the phase/frequency detector 2 in FIG. 1.
It should be noted that in some implementations it is possible to combine the initial calibration circuit and the temperature compensation circuit into a single dual-purpose circuit that serves both purposes.
There exists a need for an apparatus and method that offers a higher level of integration and does not rely on expensive high accuracy crystals. There exists a need for crystals with a specified “pull ability” combined with relatively complex circuits, and a varactor and associated circuitry for the generation of an accurate desired output frequency and channel spacing in user terminals which align appropriately with the frequencies and channel spacings of a companion base/master station.